In general, the present invention relates to a method of determining an error rate and a semiconductor integrated circuit device. More particularly, the present invention relates to an effective technology such as a data holding technology adopted in a memory circuit comprising dynamic memory cells.
As a result of a survey conducted after the present invention, Unexamined Patent Publication No. Hei 11(1999)-213659 and Unexamined Patent Publication No. Hei 7(1995)-262794 were identified. Referred to hereafter as prior art 1 and prior art 2 respectively, the former and latter publications are considered to be relevant to the present invention described later in this specification. Prior art 1 is a technology to control the frequency of refresh cycles by a CPU through execution of software using the number of erroneous rows detected by an error correction compound circuit in order to optimize intervals of refresh cycles of a DRAM in a sleep state. On the other hand, prior art 2 is a technology of detecting an error by means of an ECC circuit embedded in a DRAM and writing correction data into a memory cell.